d5f281b734
Apparently Windows 7 without SP1 has O/S support for XSAVE but not for YMM registers, and this exposed a bug in our usage of xgetbv. The test instruction will set ZF only if none of the bits match between the two operarands, so in effect, we were enabling AVX2 instructions if the O/S supported XSAVE and the CPU supported AVX2 but the O/S only supported XMM registers. This bug was not exposed on, for instance, Windows XP or RHEL 5 because those O/S's do not support XSAVE. Fixes #288
133 lines
3.7 KiB
NASM
133 lines
3.7 KiB
NASM
;
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; jsimdcpu.asm - SIMD instruction support check
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;
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; Copyright 2009 Pierre Ossman <ossman@cendio.se> for Cendio AB
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; Copyright (C) 2016, D. R. Commander.
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;
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; Based on the x86 SIMD extension for IJG JPEG library
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; Copyright (C) 1999-2006, MIYASAKA Masaru.
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; For conditions of distribution and use, see copyright notice in jsimdext.inc
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;
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; This file should be assembled with NASM (Netwide Assembler),
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; can *not* be assembled with Microsoft's MASM or any compatible
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; assembler (including Borland's Turbo Assembler).
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; NASM is available from http://nasm.sourceforge.net/ or
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; http://sourceforge.net/project/showfiles.php?group_id=6208
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;
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; [TAB8]
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%include "jsimdext.inc"
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; --------------------------------------------------------------------------
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SECTION SEG_TEXT
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BITS 32
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;
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; Check if the CPU supports SIMD instructions
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;
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; GLOBAL(unsigned int)
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; jpeg_simd_cpu_support(void)
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;
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align 32
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GLOBAL_FUNCTION(jpeg_simd_cpu_support)
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EXTN(jpeg_simd_cpu_support):
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push ebx
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; push ecx ; need not be preserved
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; push edx ; need not be preserved
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; push esi ; unused
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push edi
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xor edi, edi ; simd support flag
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pushfd
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pop eax
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mov edx, eax
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xor eax, 1<<21 ; flip ID bit in EFLAGS
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push eax
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popfd
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pushfd
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pop eax
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xor eax, edx
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jz near .return ; CPUID is not supported
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; Check for MMX instruction support
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xor eax, eax
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cpuid
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test eax, eax
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jz near .return
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xor eax, eax
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inc eax
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cpuid
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mov eax, edx ; eax = Standard feature flags
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test eax, 1<<23 ; bit23:MMX
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jz short .no_mmx
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or edi, byte JSIMD_MMX
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.no_mmx:
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test eax, 1<<25 ; bit25:SSE
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jz short .no_sse
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or edi, byte JSIMD_SSE
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.no_sse:
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test eax, 1<<26 ; bit26:SSE2
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jz short .no_sse2
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or edi, byte JSIMD_SSE2
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.no_sse2:
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; Check for AVX2 instruction support
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mov eax, 7
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xor ecx, ecx
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cpuid
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mov eax, ebx
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test eax, 1<<5 ; bit5:AVX2
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jz short .no_avx2
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; Check for AVX2 O/S support
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mov eax, 1
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xor ecx, ecx
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cpuid
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test ecx, 1<<27
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jz short .no_avx2 ; O/S does not support XSAVE
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test ecx, 1<<28
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jz short .no_avx2 ; CPU does not support AVX2
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xor ecx, ecx
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xgetbv
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and eax, 6
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cmp eax, 6 ; O/S does not manage XMM/YMM state
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; using XSAVE
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jnz short .no_avx2
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or edi, JSIMD_AVX2
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.no_avx2:
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; Check for 3DNow! instruction support
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mov eax, 0x80000000
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cpuid
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cmp eax, 0x80000000
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jbe short .return
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mov eax, 0x80000001
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cpuid
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mov eax, edx ; eax = Extended feature flags
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test eax, 1<<31 ; bit31:3DNow!(vendor independent)
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jz short .no_3dnow
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or edi, byte JSIMD_3DNOW
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.no_3dnow:
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.return:
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mov eax, edi
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pop edi
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; pop esi ; unused
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; pop edx ; need not be preserved
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; pop ecx ; need not be preserved
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pop ebx
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ret
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; For some reason, the OS X linker does not honor the request to align the
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; segment unless we do this.
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align 32
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