Reformat code per Siarhei's original patch (to clearly indicate that the offset instructions are completely independent) and add Siarhei as an individual author (he no longer works for Nokia.)
git-svn-id: svn+ssh://svn.code.sf.net/p/libjpeg-turbo/code/trunk@1388 632fc199-4ca6-4c93-a231-07263d6284db
This commit is contained in:
@@ -4,6 +4,7 @@
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* Copyright (C) 2009-2011 Nokia Corporation and/or its subsidiary(-ies).
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* Copyright (C) 2009-2011 Nokia Corporation and/or its subsidiary(-ies).
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* All rights reserved.
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* All rights reserved.
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* Author: Siarhei Siamashka <siarhei.siamashka@nokia.com>
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* Author: Siarhei Siamashka <siarhei.siamashka@nokia.com>
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* Copyright (C) 2014 Siarhei Siamashka. All Rights Reserved.
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* Copyright (C) 2014 Linaro Limited. All Rights Reserved.
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* Copyright (C) 2014 Linaro Limited. All Rights Reserved.
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*
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*
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* This software is provided 'as-is', without any express or implied
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* This software is provided 'as-is', without any express or implied
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@@ -1408,52 +1409,52 @@ asm_function jsimd_idct_2x2_neon
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.endm
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.endm
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.macro do_yuv_to_rgb_stage2_store_load_stage1
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.macro do_yuv_to_rgb_stage2_store_load_stage1
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/* "do_yuv_to_rgb_stage2" and "store" */
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/* "do_yuv_to_rgb_stage2" and "store" */
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vrshrn.s32 d20, q10, #15
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vrshrn.s32 d20, q10, #15
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/* "load" and "do_yuv_to_rgb_stage1" */
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/* "load" and "do_yuv_to_rgb_stage1" */
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pld [U, #64]
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pld [U, #64]
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vrshrn.s32 d21, q11, #15
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vrshrn.s32 d21, q11, #15
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pld [V, #64]
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pld [V, #64]
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vrshrn.s32 d24, q12, #14
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vrshrn.s32 d24, q12, #14
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vrshrn.s32 d25, q13, #14
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vrshrn.s32 d25, q13, #14
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vld1.8 {d4}, [U, :64]!
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vld1.8 {d4}, [U, :64]!
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vrshrn.s32 d28, q14, #14
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vrshrn.s32 d28, q14, #14
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vld1.8 {d5}, [V, :64]!
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vld1.8 {d5}, [V, :64]!
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vrshrn.s32 d29, q15, #14
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vrshrn.s32 d29, q15, #14
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vaddw.u8 q3, q1, d4 /* q3 = u - 128 */
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vaddw.u8 q3, q1, d4 /* q3 = u - 128 */
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vaddw.u8 q4, q1, d5 /* q2 = v - 128 */
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vaddw.u8 q4, q1, d5 /* q2 = v - 128 */
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vaddw.u8 q11, q10, d0
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vaddw.u8 q11, q10, d0
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vmull.s16 q10, d6, d1[1] /* multiply by -11277 */
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vmull.s16 q10, d6, d1[1] /* multiply by -11277 */
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vmlal.s16 q10, d8, d1[2] /* multiply by -23401 */
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vmlal.s16 q10, d8, d1[2] /* multiply by -23401 */
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vaddw.u8 q12, q12, d0
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vaddw.u8 q12, q12, d0
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vaddw.u8 q14, q14, d0
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vaddw.u8 q14, q14, d0
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.if \bpp != 16 /**************** rgb24/rgb32 *********************************/
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.if \bpp != 16 /**************** rgb24/rgb32 *********************************/
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vqmovun.s16 d1\g_offs, q11
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vqmovun.s16 d1\g_offs, q11
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pld [Y, #64]
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pld [Y, #64]
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vqmovun.s16 d1\r_offs, q12
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vqmovun.s16 d1\r_offs, q12
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vld1.8 {d0}, [Y, :64]!
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vld1.8 {d0}, [Y, :64]!
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vqmovun.s16 d1\b_offs, q14
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vqmovun.s16 d1\b_offs, q14
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vmull.s16 q11, d7, d1[1] /* multiply by -11277 */
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vmull.s16 q11, d7, d1[1] /* multiply by -11277 */
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vmlal.s16 q11, d9, d1[2] /* multiply by -23401 */
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vmlal.s16 q11, d9, d1[2] /* multiply by -23401 */
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do_store \bpp, 8
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do_store \bpp, 8
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vmull.s16 q12, d8, d1[0] /* multiply by 22971 */
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vmull.s16 q12, d8, d1[0] /* multiply by 22971 */
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vmull.s16 q13, d9, d1[0] /* multiply by 22971 */
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vmull.s16 q13, d9, d1[0] /* multiply by 22971 */
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vmull.s16 q14, d6, d1[3] /* multiply by 29033 */
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vmull.s16 q14, d6, d1[3] /* multiply by 29033 */
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vmull.s16 q15, d7, d1[3] /* multiply by 29033 */
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vmull.s16 q15, d7, d1[3] /* multiply by 29033 */
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.else /**************************** rgb565 ***********************************/
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.else /**************************** rgb565 ***********************************/
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vqshlu.s16 q13, q11, #8
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vqshlu.s16 q13, q11, #8
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pld [Y, #64]
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pld [Y, #64]
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vqshlu.s16 q15, q12, #8
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vqshlu.s16 q15, q12, #8
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vqshlu.s16 q14, q14, #8
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vqshlu.s16 q14, q14, #8
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vld1.8 {d0}, [Y, :64]!
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vld1.8 {d0}, [Y, :64]!
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vmull.s16 q11, d7, d1[1]
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vmull.s16 q11, d7, d1[1]
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vmlal.s16 q11, d9, d1[2]
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vmlal.s16 q11, d9, d1[2]
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vsri.u16 q15, q13, #5
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vsri.u16 q15, q13, #5
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vmull.s16 q12, d8, d1[0]
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vmull.s16 q12, d8, d1[0]
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vsri.u16 q15, q14, #11
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vsri.u16 q15, q14, #11
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vmull.s16 q13, d9, d1[0]
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vmull.s16 q13, d9, d1[0]
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vmull.s16 q14, d6, d1[3]
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vmull.s16 q14, d6, d1[3]
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do_store \bpp, 8
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do_store \bpp, 8
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vmull.s16 q15, d7, d1[3]
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vmull.s16 q15, d7, d1[3]
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.endif
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.endif
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.endm
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.endm
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