Fix segfault in MIPS DSPr2 upsample routines that occurred when doing 'make test'
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@@ -486,7 +486,6 @@ LEAF_MIPS_DSPR2(jsimd_h2v1_fancy_upsample_mips_dspr2)
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nop
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nop
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END(jsimd_h2v1_fancy_upsample_mips_dspr2)
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END(jsimd_h2v1_fancy_upsample_mips_dspr2)
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/*****************************************************************************/
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/*****************************************************************************/
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/*****************************************************************************/
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LEAF_MIPS_DSPR2(jsimd_h2v1_downsample_mips_dspr2)
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LEAF_MIPS_DSPR2(jsimd_h2v1_downsample_mips_dspr2)
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/*
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/*
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@@ -704,15 +703,15 @@ LEAF_MIPS_DSPR2(jsimd_h2v1_upsample_mips_dspr2)
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lw t7, 0(a3) // t7 = output_data
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lw t7, 0(a3) // t7 = output_data
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andi t8, a1, 0xf // t8 = residual
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andi t8, a1, 0xf // t8 = residual
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sll t0, a0, 2
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sll t0, a0, 2
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beqz a0, 4f
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blez a0, 4f
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addu t9, t7, t0 // t9 = output_data end address
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addu t9, t7, t0 // t9 = output_data end address
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0:
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0:
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lw t5, 0(t7) // t5 = outptr
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lw t5, 0(t7) // t5 = outptr
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lw t6, 0(a2) // t6 = inptr
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lw t6, 0(a2) // t6 = inptr
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addu t3, t5, a1 // t3 = outptr + output_width (end address)
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addu t3, t5, a1 // t3 = outptr + output_width (end address)
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subu t3, t8 // t3 = end address - residual
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subu t3, t8 // t3 = end address - residual
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beqz t3, 2f
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beq t5, t3, 2f
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nop
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move t4, t8
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1:
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1:
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ulw t0, 0(t6) // t0 = |P3|P2|P1|P0|
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ulw t0, 0(t6) // t0 = |P3|P2|P1|P0|
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ulw t2, 4(t6) // t2 = |P7|P6|P5|P4|
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ulw t2, 4(t6) // t2 = |P7|P6|P5|P4|
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@@ -761,15 +760,15 @@ LEAF_MIPS_DSPR2(jsimd_h2v2_upsample_mips_dspr2)
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* a3 - output_data_ptr
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* a3 - output_data_ptr
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*/
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*/
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lw t7, 0(a3)
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lw t7, 0(a3)
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beqz a0, 7f
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blez a0, 7f
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andi t9, a1, 0xf // t9 = residual
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andi t9, a1, 0xf // t9 = residual
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0:
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0:
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lw t6, 0(a2) // t6 = inptr
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lw t6, 0(a2) // t6 = inptr
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lw t5, 0(t7) // t5 = outptr
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lw t5, 0(t7) // t5 = outptr
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addu t8, t5, a1 // t8 = outptr end address
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addu t8, t5, a1 // t8 = outptr end address
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subu t8, t9 // t8 = end address - residual
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subu t8, t9 // t8 = end address - residual
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beqz t8, 2f
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beq t5, t8, 2f
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nop
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move t4, t9
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1:
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1:
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ulw t0, 0(t6)
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ulw t0, 0(t6)
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srl t1, t0, 16
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srl t1, t0, 16
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